The present invention relates to a complementary logic circuit, more precisely, to a complementary IC (Integrated Circuit) which enables a high speed switching of signals at high current level without increasing power consumption. The circuit of the present invention is provided with pull-up or pull-down elements which pull up or pull down the level of the output signal to a value close to that of the power supply voltage. The circuit is realized by combining MIS (Metal Insulator Semiconductor) transistors and bipolar transistors or vertical FETs (Field Effect Transistors).
A complementary MIS (C-MIS) type logic circuit is widely used as a very low power consumption circuit, but it has disadvantages of a rather low switching speed and a rather low power handling capacity. Therefore, it was difficult to drive large scale and complicated logic circuits with C-MIS.
There were attempts to overcome such defects of the complementary MIS circuit by combining MIS-FETs with bipolar transistors, especially a vertical type bipolar transistor, which has high speed and high power handling capacity. Such circuits are sometimes called Bi-MIS circuits and are used widely (for example, U.S. patent application No. 373,845 which is laid open in Japan with Provisional Publication No. 38454/'75, by C. H. Grady). But there appeared other difficulties with such improved circuits, as will be described later, and the improvement was inadequate. The problem was imposed mainly by the lack of signal amplitude sufficient to operate a large and complicated C-MIS circuit. The insufficient signal level caused a slightly-ON state in the C-MIS logic circuit which is driven by the Bi-MIS circuit. Another problem was a rush current which runs through the bipolar transistors at the transient of switching. These increased the quiescent current and temperature of the IC chip, and the increased temperature imposed undesirable effects on the reliability of the devices.